1. Technical Field
The invention relates to an integrated circuit arrangement containing a substrate. In particular, the invention relates to an integrated circuit arrangement with a capacitor in an interconnect layer.
2. Background Information
In copper metallizations produced by the damascene method, the conductive structure layers in each case have even bottom areas and even top areas. This arrangement applies to aluminum metallizations produced using polishing methods. Copper metallizations comprise copper or a copper alloy with at least 90 atomic percent copper. Aluminum metallizations comprise aluminum or an aluminum alloy with at least 90 atomic percent aluminum. The conductive structures are differentiated for example as vias for vertical current transport and interconnects for lateral current transport.